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| &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf power connections follow the conventional descriptions be- low: %qppgevkqp %ktewkv &gxkeg 2qygt 8 %% 8 && )tqwpf )0& 8 55 (kiwtg <5<.(wpevkqpcn$nqem&kcitco 2*+ #fftguu$wu $kv &cvc$wu $kv 4'5'6 4& 94 / /4'3 +143 *#.6 9#+6 $754'3 $75#%- 4(5* 56 ' 0/+ +06 +06 +06 ':6#. :6#. &4'3 6:# %-#&4'3 4:# 465 %65 &%& 6:# %-#6'0& 4:# 8 && 8 55 & & # # #fftguu $whhgt &cvc $whhgt #u[pejtqpqwu 5%+ %jcppgn #u[pejtqpqwu 5%+ %jcppgn &/#%u %27 %-5 4:5 %65 6:5 #6 176 $kv 6'0& 2tqitcoocdng 4gnqcf6kogtu %nqemgf 5gtkcn+1 2qtv 6kokpi )gpgtcvqt $wu5vcvg%qpvtqn +pvgttwrv //7 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf (kiwtg <5<.2kp2.%%2kp%qphkiwtcvkqp 0/+ 4'5'6 $754'3 $75#%- 9#+6 ':6#. :6#. 8 5 5 8 5 5 2*+ 4& 94 / ' /4'3 +143 4(5* +06 +06 +06 56 # # # # 8 55 # # # # # # # # <5<. 2kp2.%% *#.6 6'0& &4'3 %-5 4:5%65 6:5 %-#6'0& 4:# 6'56 6:# %-#&4'3 4:# 6:# &%& %65 465 & # # # # # # #6 1 7 6 8 & & # 8 5 5 & & & & & & & <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf # 0% # # # # # # # 0% 0% # # # # # # 0% # 6 176 $kvqt$kvqh6%4 8 && # 8 55 & & & & & & & 0% 0% & 465 %65 &%& 6:# 4:# %-# &4'3 $kvqt$kvqh&/1&' 0% 6:# 6cdng <5<.2kp+fgpvkhkecvkqp %qpvkpwgf 2kp0wodgtcpf2cemcig6[rg &ghcwnv (wpevkqp 5geqpfct[ (wpevkqp %qpvtqn 3(2 2.%% &+2 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5%qpvkpwgf 2kp0wodgtcpf2cemcig6[rg &ghcwnv (wpevkqp 5geqpfct[ (wpevkqp %qpvtqn 3(2 2.%% &+2 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf 6cdng 2kp5vcvwu&wtkpi4'5'6$75#%-cpf5.''2/qfgu 2kp0wodgtcpf2cemcig6[rg 2kp5vcvwu 3(2 2.%% &+2 &ghcwnv (wpevkqp 5geqpfct[ (wpevkqp 4'5'6 $75#%- 5.''2 0/+ +0 +0 +0 0% 0% +06 +0 +0 +0 +06 +0 +0 +0 +06 +0 +0 +0 56 *kij *kij *kij # 6 6*kij # 6 6*kij # 6 6 *kij # 6 6 *kij 8 55 8 55 8 55 8 55 # 6 6 *kij 0% # 6 6 *kij # 6 6 *kij # 6 6 *kij # 6 6 *kij # 6 6 *kij # 6 6 *kij # 6 6 *kij 0% 0% # 6 6 *kij # 6 6 *kij # 6 6 *kij # 6 6 *kij # 6 6 *kij # 6 6 *kij 0% # 6 6 *kij 6 176 0# 176 176 8 && 8 && 8 && 8 && # 6 6 *kij 8 55 8 55 8 55 8 55 & 6 6 6 & 6 6 6 & 6 6 6 & 6 6 6 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5%qpvkpwgf 2kp0wodgtcpf2cemcig6[rg 2kp5vcvwu 3(2 2.%% &+2 &ghcwnv (wpevkqp 5geqpfct[ (wpevkqp 4'5'6 $75#%- 5.''2 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf ':6#. +0 +0 +0 9#+6 +0 +0 +0 $75#%- *kij 176 176 $754'3 +0 +0 +0 4'5'6 +0 +0 +0 6cdng 2kp5vcvwu&wtkpi4'5'6$75#%-cpf5.''2/qfgu %qpvkpwgf 2kp0wodgtcpf2cemcig6[rg 2kp5vcvwu 3(2 2.%% &+2 &ghcwnv (wpevkqp 5geqpfct[ (wpevkqp 4'5'6 $75#%- 5.''2 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf ways recognized at the end of an instruction, regardless of the state of the interrupt-enable flip-flops. this signal forces cpu execution to continue at location 0066h . 2*+ system clock (output). the output is used as a refer- ence clock for the mpu and the external system. the fre- quency of this output may be one-half, equal to, or twice the crystal or input clock frequency. 4& read (output, active low, 3-state). 4& indicates that the cpu wants to read data from either memory or an i/o device. the addressed i/o or memory device should use this signal to gate data onto the cpu data bus. 4(5* refresh (output, active low). together with /4'3 , 4(5* indicates that the current cpu machine cycle and the contents of the address bus should be used for refresh of dy- namic memories. the low-order 8 bits of the address bus ( # # ) contain the refresh address. this signal is analogous to the ref signal of the z64180. 465 request to send 0 (output, active low); a program- mable modem control signal for asci channel 0. 4:#4:# receive data 0 and 1 (input). these signals are the receive data for the asci channels. 4:5 clocked serial receive data (input). this line is the receive data for the csi/o channel. rxs is multiplexed with the %65 signal for asci channel 1. 56 status (output). this signal is used with the / and *#.6 output to decode the status of the cpu machine cycle. see table 3. 6'0& 6'0& transfer end 0 and 1 (outputs, active low). this output is asserted active during the most recent 94+6' cycle of a dma operation. it is used to indicate the end of the block transfer. 6'0& is multiplexed with %-# . 6'56 test (output, not in dip version). this pin is for test and should be left open. 6 176 timer out (output). 6 176 is the output from prt channel 1. this line is multiplexed with # of the address bus. 6:#6:# transmit data 0 and 1 (outputs). these sig- nals are the transmitted data from the asci channels. trans- mitted data changes are with respect to the falling edge of the transmit clock. 6:5 clocked serial transmit data (output). this line is the transmitted data from the csi/o channel. 9#+6 . wait (input, active low). 9#+6 indicates to the mpu that the addressed memory or i/o devices are not ready for data transfer. this input is sampled on the falling edge of 6 (and subsequent 9#+6 states). if the input is sampled low, then the additional 9#+6 states are inserted until the 9#+6 input is sampled high, at which time exe- cution continues. 94 . 94+6' (output, active low, 3-state). 94 indicates that the cpu data bus holds valid data to be stored at the ad- dressed i/o or memory location. :6#. crystal oscillator connection (input). this pin should be left open if an external clock is used instead of a crystal. the oscillator input is not a ttl level (see dc char- acteristics ). several pins are used for different conditions, depending on the circumstance. 6cdng 5vcvwu5wooct[ 56 *#.6 / 1rgtcvkqp %271rgtcvkqp uv1reqfg(gvej %271rgtcvkqp pf1reqfgcpftf 1reqfg(gvej %271rgtcvkqp /%'zegrv1reqfg (gvej :&/#1rgtcvkqp *#.6/qfg 5.''2/qfg +penwfkpi5;56'/ 5612/qfg notes: : &qpqvectg /% /cejkpg%[eng <5<. zilog 'pjcpegf</ketqrtqeguuqt &56%4 kuugvvq 1 vjg6 176 hwpevkqpkuugngevgf+h61%cpf61%ctgengctgf vq 0 vjg#hwpevkqpkuugngevgf %-#&4'3 &wtkpi4'5'6vjkurkpkukpkvkcnk\gfcu%-#+hgkvjgt&/qt5/kpvjg&/#/qfgtgikuvgt &/1&' kuugvvq 1 vjg&4'3 hwpevkqpkuugngevgf %-#6'0& &wtkpi4'5'6vjkurkpkukpkvkcnk\gfcu%-#+hvjg%-#&dkvkp#5%+eqpvtqntgikuvgtej %06.# kuugvvq 1 vjg6'0& hwpevkqpkuugngevgf+hvjg%-#&dkvkuugvvq 0 vjg%-# hwpevkqpkuugngevgf 4:5%65 &wtkpi4'5'6vjkurkpkukpkvkcnk\gfcu4:5+hvjg%65'dkvkpvjg#5%+uvcvwutgikuvgtej 56#6 kuugvvq 1 vjg%65 hwpevkqpkuugngevgf+hvjg%65'dkvkuugvvq 0 vjg4:5 hwpevkqpkuugngevgf <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5#5%+ the asci logic provides two individual full-duplex uarts. each channel includes a programmable baud rate generator and modem control signals. the asci channels can also support a multiprocessor communication format as well as break detection and generation 2tqitcoocdng4gnqcf6kogtu 246 this logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. the time base for the counters is derived from the system clock (divided by 20) before reaching the counter. prt channel 1 provides an op- tional output to allow for waveform generation. <5<. zilog 'pjcpegf</ketqrtqeguuqt &5%5+1 the csi/o channel provides a half-duplex serial transmitter and receiver. this channel can be used for simple high-speed data connection to an- other microprocessor or microcomputer. 64&4 is used for both csi/o transmission and reception. thus, the system design must ensure that the constraints of half-duplex op- eration are met (transmit and receive operation cannot oc- cur simultaneously). for example, if a csi/o transmission is attempted while the csi/o is receiving data, a csi/o does not work. 0qvg 64&4 is not buffered. performing a csi/o transmit while the previous transmission is still in progress causes the data to be immediately updated and corrupts the transmit operation. similarly, reading 64&4 while a transmit or receive is in progress should be avoided. (kiwtg 6kogt+pkvkcnk\cvkqp%qwpv&qypcpf4gnqcf6kokpi (kiwtg 6kogt1wvrwv6kokpi ((((* * * * * * * * * * * 6kogt&cvc4gikuvgt 9tkvg * 6kogt&cvc 4gikuvgt 6kogt4gnqcf 4gikuvgt 6&'(nci 6+((nci 4gugv f f f f f f f f f v f 6kogt4gnqcf4gikuvgt9tkvg * ((((* * 4gnqcf 4gnqcf 9tkvgvq6&' 6kogt&cvc4gikuvgt4gcf 6kogt%qpvtqn4gswguvqt4gcf 6kogt&cvc 4gi * 6kogt&cvc 4gi * 6 176 2*+ <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf (kiwtg %5+1$nqem&kcitco +pvgtpcn#fftguu&cvc$wu %5+16tcpuokv4gegkxg &cvc4gikuvgt 64&4 %5+1%qpvtqn4gikuvgt %064 $cwf4cvg )gpgtcvqt 6:5 4:5 %-5 +pvgttwrv4gswguv 2*+ <5<. zilog 'pjcpegf</ketqrtqeguuqt &5/ 'pcdng this bit controls the / output and is set to a 1 during 4'5'6 . when /' 1 , the / output is asserted low during op- code fetch cycles, interrupt acknowledge cycles, and the first machine cycle of an 0/+ acknowledge. on the z8s180/z8l180, this choice makes the processor fetch a 4'6+ instruction one time. when fetching a 4'6+ from a zero-wait-state memory location, the processor uses three clock bus cycles. these bus cycles are not fully z80- timing compatible. when /' 0 , the processor does not drive / low dur- ing the instruction fetch cycles. after fetching a 4'6+ in- struction with normal timing, the processor goes back and refetches the instruction using fully z80-compatible cycles that include driving / low. this option may be required by some external z80 peripherals to properly decode the 4'6+ instruction. figure 9 and table 5 show the 4'6+ se- quence when /' is 0 . (kiwtg 1rgtcvkpi%qpvtqn4gikuvgt 1/%4 +1#fftguu '* & 4gugtxgf & & /' 49 +1% 49 /6' 9 (kiwtg 4'6++puvtwevkqp5gswgpegykvj/' 6 6 6 6 6 6 6 + 6 + 6 + 6 6 6 6 6 6 6 + 6 + # # # & & 2% 2% 2% 2% '&* &* '&* &* /4'3 4& 56 / 2*+ <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf /6' / 6gorqtct['pcdng this bit controls the tem- porary assertion of the / signal. it is always read back as a 1 and is set to 1 during 4'5'6 . when /' is set to 0 to accommodate certain external z80 peripheral(s), those same device(s) may require a pulse on / after programming certain of their registers to complete the function being programmed. for example, when a control word is written to the z80 pio to enable interrupts, no enable actually takes place until the pio sees an active / signal. when /6' = 1 , there is no change in the operation of the / signal, and /' controls its function. when /6' = 0 , the / output is asserted dur- ing the next opcode fetch cycle regardless of the state pro- grammed into the /' bit. this condition is only momen- tary (one time) and it is not necessary to preprogram a 1 to disable the function (see figure 10). +1% +1%qorcvkdknkv[ this bit controls the timing of the +143 and 4& signals. the bit is set to 1 by 4'5'6 . when +1% = 1 , the +143 and 4& signals function the same as the z64180 (figure 11). 6cdng 4'6+%qpvtqn5kipcn5vcvgu /cejkpg %[eng 5vcvgu #fftguu &cvc 4& 94 /4'3 +143 / /' / /' *#.6 56 6 6 uv1reqfg '&* 6 6 pf1reqfg &* 6k 0# uvcvg 6k 0# uvcvg 6k 0# uvcvg 6 6 uv1reqfg '&* 6k 0# uvcvg 6 6 pf1reqfg &* 6 6 52 &cvc 6 6 52 &cvc (kiwtg /6gorqtct['pcdng6kokpi 6 6 6 6 6 6 94 / 1reqfg(gvej 9tkvgkpvq1/%4 2*+ <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf the z8s180/z8l180 leaves *#.6 mode in response to: low on 4'5'6 interrupt from an enabled on-chip source external request on 0/+ enabled external request on +06 , +06 , or +06 in case of an interrupt, the return address is the instruction following the *#.6 instruction. the program can either branch back to the *#.6 instruction to wait for another in- terrupt or can examine the new state of the system/applica- tion and respond appropriately. 5.''2/qfg this mode is entered by keeping the +15612 bit (icr5) and bits 3 and 6 of the cpu control register (ccr3, ccr6) all zero and executing the 5.2 instruction. the oscillator and 2*+ output continue operating, but are blocked from the cpu core and dma channels to reduce power consumption. dram refresh stops, but interrupts and granting to an external master can occur. except when the bus is granted to an external master, a19C0 and all con- trol signals except *#.6 are maintained high. *#.6 is low. i/o operations continue as before the 5.2 instruction, except for the dma channels. the z8s180/z8l180 leaves 5.''2 mode in response to a low on 4'5'6 , an interrupt request from an on-chip source, an external request on 0/+ , or an external request on +06 , +06 , or +06 . if an interrupt source is individually disabled, it cannot bring the z8s180/z8l180 out of 5.''2 mode. if an interrupt source is individually enabled, and the +'( bit is 1 so that interrupts are globally enabled (by an ei instruction), the highest priority active interrupt occurs with the return ad- dress being the instruction after the 5.2 instruction. if an interrupt source is individually enabled, but the +'( bit is 0 so that interrupts are globally disabled (by a di instruction), the z8s180/z8l180 leaves 5.''2 mode by simply execut- ing the following instruction(s). (kiwtg *#.66kokpi int , nmi a ? halt m1 mreq rd note: phi t 19 0 i halt opcode fetch cycle halt opcode address halt opcode address + 1 halt mode interrupt acknowledge cycle 2 t 3 t 1 t 2 indicates an indefinite delay. <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf while the z8s180/z8l180 is in +&.' mode, it grants the bus to an external master if the brext bit (ccr5) is 1 . figure 16 depicts the timing for this sequence. 0qvg a response to a bus request takes 8 clock cycles longer than in normal operation. after the external master negates the bus request, the z8s180/z8l180 disables the 2*+ clock and remains in +&.' mode. (kiwtg <5<.+&.'/qfg'zkv&wg6q'zvgtpcn+pvgttwrv 2*+ 6 6 6 0/+ # # *#.6 / 1reqfg(gvejqt+pvgttwrv #empqyngfig%[eng (((((* +&.'/qfg 6 %[eng&gnc[htqo+06k #uugtvgf +06 +06 +06 qt <5<. zilog 'pjcpegf</ketqrtqeguuqt &59kvjqt9kvjqwv37+%-4'%18'4; software can put the z8s180/z8l180 into this mode by set- ting the +15612 bit (icr5) to 1 , ccr6 to 1 , and executing the 5.2 instruction. this mode stops the on-chip oscillator and thus draws the least power of any mode, less than 10a. as with +&.' mode, the z8s180/z8l180 leaves 56#0&$; mode in response to a low on 4'5'6 , on 0/+ , or a low on +06 C2 that is enabled by a 1 in the corresponding bit in the int/trap control register. this action grants the bus to an external master if the brext bit in the cpu con- trol register (ccr5) is 1 . the time required for all of these operations is greatly increased by the necessity for restart- ing the on-chip oscillator, and ensuring that it stabilizes to square-wave operation. when an external clock is connected to the extal pin rath- er than a crystal to the xtal and extal pins and the ex- ternal clock runs continuously, there is little necessity to use 56#0&$; mode because no time is required to restart the oscillator, and other modes restart faster. however, if ex- ternal logic stops the clock during 56#0&$; mode (for ex- ample, by decoding *#.6 low and / high for several clock cycles), then 56#0&$; mode can be useful to allow the external clock source to stabilize after it is re-enabled. when external logic drives 4'5'6 low to bring the device out of 56#0&$; mode, and a crystal is in use or an external clock source is stopped, the external logic must hold 4'5'6 low until the on-chip oscillator or external clock source is restarted and stabilized. the clock-stability requirements of the z8s180/z8l180 are much less in the divide-by-two mode that is selected by a 4'5'6 sequence and controlled by the clock divide bit in the cpu control register (ccr7). as a result, software per- forms the following actions: 1. sets ccr7 to 0 for divide-by-two mode before an 5.2 instruction and 56#0&$; mode. 2. delays setting ccr7 back to 1 for divide-by-one mode as long as possible to allow additional clock stabilization time after a 4'5'6 , interrupt, or in-line restart after an 5.2 01 instruction. if ccr6 is set to 1 before the 5.2 instruction places the mpu in 56#0&$; mode, the value of the ccr3 bit deter- mines the length of the delay before the oscillator restarts and stabilizes when it leaves 56#0&$; mode due to an ex- ternal interrupt request. when ccr3 is 0 , the z8s180/z8l180 waits 2 17 (131,072) clock cycles. when ccr3 is 1 , it waits 64 clock cycles. this state is called 37+%-4'%18'4; mode. the same delay applies to grant- (kiwtg $wu)tcpvkpivq'zvgtpcn/cuvgtkp+&.'/qfg 2*+ 6: $754'3 # # *#.6 / $wu4gngcug/qfg +&.'/qfg (((((* +&.'/qfg %[eng&gnc[wpvkn$75#%- #uugtvgf $75#%- 6: *kij+orgfcpeg (((((* *kij .qy <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5 <5<. zilog 'pjcpegf</ketqrtqeguuqt &50qtocn1rgtcvkqp ( /*\ o# 2qygt&kuukrcvkqp 5;56'/5612oqfg ( /*\ % 2 2kp%crcekvcpeg 8 +0 8 h /*\ 6 # u% r( 0qvg 8 +*okp 8 && 88 +.ocz 8 #nnqwvrwvvgtokpcnuctgcv01.1#& 8 && 8 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &50qtocn1rgtcvkqp ( /*\ o# /*\ 2qygt&kuukrcvkqp 5;56'/5612oqfg ( /*\ /*\ % 2 2kp%crcekvcpeg 8 +0 8h /*\ 6 # u% r( 0qvg 8 +*okp 8 && 88 +.ocz 8 #nnqwvrwvvgtokpcnuctgcv01.1#& 8 && 8 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5/goqt[9tkvg%[eng pu c 94 2wnug9kfvj +19tkvg%[eng pu v 9&* 9tkvg&cvc*qnf6koghtqo94 4kug pu v +1& 2*+(cnnvq+143 (cnn&gnc[ +1% pu 2*+4kugvq+143 (cnn&gnc[ +1% v +1& 2*+(cnnvq+143 4kug&gnc[ pu v +1& / (cnnvq+143 (cnn&gnc[ pu v +065 +06 5gvwr6kogvq2*+(cnn pu <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf v +06* +06 *qnf6koghtqo2*+(cnn pu v 0/+9 0/+ 2wnug9kfvj pu v $45 $754'3 5gvwr6kogvq2*+(cnn pu v $4* $754'3 *qnf6koghtqo2*+(cnn pu v $#& 2*+4kugvq$75#%- (cnn&gnc[ pu v $#& 2*+(cnnvq$75#%- 4kug&gnc[ pu v $<& 2*+4kugvq$wu(nqcvkpi&gnc[6kog pu v /'9* /4'3 2wnug9kfvj *kij pu v /'9. /4'3 2wnug9kfvj .qy pu v 4(& 2*+4kugvq4(5* (cnn&gnc[ pu v 4(& 2*+4kugvq4(5* 4kug&gnc[ pu v *#& 2*+4kugvq*#.6 (cnn&gnc[ pu v *#& 2*+4kugvq*#.6 4kug&gnc[ pu v &435 &4'3 5gvwr6kogvq2*+4kug pu v &43* &4'3 *qnf6koghtqo2*+4kug pu v 6'& 2*+(cnn vq6'0&k (cnn &gnc[ pu v 6'& 2*+(cnnvq6'0&k 4kug &gnc[ pu v '& 2*+4kug vq'4kug &gnc[ pu v '& 2*+(cnnqt4kug vq'(cnn &gnc[ pu 2 9'* '2wnug9kfvj *kij pu 2 9'. '2wnug9kfvj .qy pu v 't 'pcdng4kug6kog pu v 'h 'pcdng(cnn6kog pu v 61& 2*+(cnn vq6kogt1wvrwv&gnc[ pu v 56&+ %5+16tcpuokv&cvc&gnc[6kog +pvgtpcn %nqem1rgtcvkqp ve[e v 56&' %5+16tcpuokv&cvc&gnc[6kog 'zvgtpcn %nqem1rgtcvkqp v %;% v %;% pu v 545+ %5+14gegkxg&cvc5gvwr6kog +pvgtpcn %nqem1rgtcvkqp ve[e v 54*+ %5+14gegkxg&cvc*qnf6kog +pvgtpcn %nqem1rgtcvkqp ve[e v 545' %5+14gegkxg&cvc5gvwr6kog 'zvgtpcn %nqem1rgtcvkqp ve[e v 54*' %5+14gegkxg&cvc*qnf6kog 'zvgtpcn %nqem1rgtcvkqp ve[e v 4'5 4'5'6 5gvwr6kogvq2*+(cnn pu 6cdng <5#%%jctcevgtkuvkeu %qpvkpwgf 8 && 8vqt8 && 8v /*\%jctcevgtkuvkeu#rrn[1pn[vq81rgtcvkqp 0wodgt 5[odqn +vgo <5 /*\ <5 /*\ 7pkv /kp /cz /kp /cz <5<. zilog 'pjcpegf</ketqrtqeguuqt &5':6#. pu v ':( 'zvgtpcn%nqem(cnn6kog ':6#. pu v 44 4'5'6 4kug6kog ou v 4( 4'5'6 (cnn6kog ou v +4 +prwv4kug6kog gzegrv':6#.4'5'6 pu v +( +prwv(cnn6kog gzegrv':6#.4'5'6 pu 6cdng <5#%%jctcevgtkuvkeu %qpvkpwgf 8 && 8vqt8 && 8v /*\%jctcevgtkuvkeu#rrn[1pn[vq81rgtcvkqp 0wodgt 5[odqn +vgo <5 /*\ <5 /*\ 7pkv /kp /cz /kp /cz <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &51reqfg(gvej%[eng/goqt[4gcf%[eng /goqt[9tkvg%[eng+19tkvg %[eng +1 4gcf%[eng 2*+ #&&4'55 9#+6 /4'3 +143 4& 94 / 56 &cvc+0 &cvc176 4'5'6 1reqfg(gvej%[eng 6 +19tkvg%[eng +14gcf%[eng 6 6 9 6 6 6 6 9 6 6 0qvg /goqt[4gcf9tkvg%[engvkokpikuvjgucogcu+1 4gcf9tkvg%[enggzegrvvjgtgctgpqcwvqocvkeyckv uvcvgu 6 9 cpf/4'3 kucevkxgkpuvgcfqh+143 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5+06 #empqyngfig%[eng4ghtguj%[eng$754'.'#5'/qfg *#.6/qfg5.''2/qfg5;56'/5612/qfg 2*+ +06 0/+ / +143 &cvc+0 /4'3 4(5* $754'3 $75#%- /4'3 4& 94 +143 *#.6 1wvrwv$whhgt1hh # & <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf (kiwtg %276kokpi +1% +14gcf%[eng+19tkvg%[eng (kiwtg &/#%qpvtqn5kipcnu 6 6 6 y 6 6 6 6 y 6 #&&4'55 2*+ 4& +143 94 +14gcf%[eng +19tkvg%[eng %276kokpi +1% +14gcf%[eng +19tkvg%[eng ngxgnugpug &4'3 gfigugpug 6'0&k 56 2*+ 6 6 6 9 6 6 &4'3 %27qt&/#4gcf9tkvg%[eng 1pn[&/#9tkvg%[enghqt6'0&k %27%[eng 5vctvu &/#%[eng 5vctvu 0qvgu 6 &435 cpf6 &43* ctgurgekhkgfhqtvjgtkukpigfigqhvjgenqemhqnnqygfd[6 6 &435 cpf6 &43* ctgurgekhkgfhqtvjgtkukpigfigqhvjgenqem <5<. zilog 'pjcpegf</ketqrtqeguuqt &5/goqt[4gcf9tkvg%[eng+14gcf9tkvg%[eng (kiwtg '%nqem6kokpi $754'.'#5'/qfg5.''2/qfg5;56'/5612/qfg (kiwtg '%nqem6kokpi /kpkowo6kokpi'zcorngqh2 9'. cpf2 9'* & & ' /goqt[4gcf9tkvg ' +14gcf ' +19tkvg 2*+ ` ` ` ` ` ` ` ` ` ` ` ` 6 6 6 9 6 9 6 2*+ ' $754'.'#5'oqfg 5.''2oqfg 5;56'/5612oqfg 6 6 6 9 6 6 ' 'zcorng +14gcf ? 1reqfg(gvej 2*+ ' +19tkvg <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf (kiwtg 6kogt1wvrwv6kokpi (kiwtg 5.2'zgewvkqp%[eng 6kogt&cvc 4gi * # 6 176 2*+ # # 5.2+puvtwevkqp(gvej /4'3 / 0/+ +06k *#.6 2*+ ` ` ` ` ` ` ` ` ` ` 6 6 6 5 6 5 6 6 6 4& 0gzv1reqfg(gvej ` ` ` ` <5<. zilog 'pjcpegf</ketqrtqeguuqt &5'zvgtpcn%nqem 6tcpuokv&cvc +pvgtpcn%nqem 4gegkxg&cvc 'zvgtpcn%nqem 4gegkxg&cvc +pvgtpcn%nqem %5+1%nqem 8 +. 8 +* ':6#.8 +. 8 +* 'zvgtpcn%nqem4kug6kog cpf(cnn6kog +prwv4kug6kogcpf(cnn6kog 'zegrv':6#.4'5'6 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%%4 this register controls the basic clock rate, certain aspects of power-down modes, and output drive/low-noise options (figure 31). $kv clock divide select. if this bit is 0 , as it is after a 4' 5'6 , the z8s180/z8l180 divides the frequency on the :6#. pin(s) by two to obtain its master clock 2*+ . if this bit is programmed as 1 , the part uses the :6#. frequency as 2*+ without division. if an external oscillator is used in divide-by-one mode, the minimum pulse width requirement provided in the ac characteristics must be satisfied. $kvucpf 56#0&$; / +&.' control. when these bits are both 0 , a 5.2 instruction makes the z8s180/z8l180 en- ter 5.''2 or 5;56'/5612 mode, depending on the +15612 bit (icr5). when d6 is 0 and d3 is 1 , setting the +15612 bit (icr5) and executing a 5.2 instruction puts the z8s180/z8l180 into +&.' mode in which the on-chip oscillator runs, but its output is blocked from the rest of the part, including 2*+ out. when d6 is 1 and d3 is 0 , setting +15612 (icr5) and executing a 5.2 instruction puts the part into 56#0&$; mode, in which the on-chip oscillator is stopped and the part allows 2 17 (128k) clock cycles for the oscillator to stabilize when it restarts. when d6 and d3 are both 1 , setting +15612 ( +%4 ) and executing a 5.2 instruction puts the part into 37+%-4' %18'4; 56#0&$; mode, in which the on-chip oscillator is stopped, and the part allows only 64 clock cycles for the oscillator to stabilize when it restarts. the latter section, *#.6 and .19219'4 modes, de- scribes the subject more fully. $kv $4':6 this bit controls the ability of the z8s180/z8l180 to honor a bus request during 56#0&$; mode. if this bit is set to 1 and the part is in 56#0&$; mode, a $754'3 is honored after the clock stabilization timer is timed out. $kv.02*+ this bit controls the drive capability on the 2*+ clock output. if this bit is set to 1 , the 2*+ clock output is reduced to 33 percent of its drive capability. (kiwtg %27%qpvtqn4gikuvgt %%4 #fftguu(* & .0#&# & & & & & & & %27%qpvtqn4gikuvgt %%4 5vcpfctf&tkxg &tkxgqp # #& & .0%27%6. 5vcpfctf&tkxg &tkxgqp%27 %qpvtqn5kipcnu .0+1 5vcpfctf&tkxg &tkxgqp )tqwr+15kipcnu .02*+ 5vcpfctf&tkxg &tkxgqp 2*+2kp %nqem&kxkfg :6#. :6#. 56#0&$;+&.''pcdng 0q56#0&$; +&.'#hvgt5.''2 56#0&$;#hvgt5.''2 56#0&$;#hvgt5.''2 %[eng'zkv 37+%-4'%18'4; $4':6 +ipqtg$754'3 qp56#0&$;+&.' 56#0&$;+&.''zkv qp$754'3 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &56&4 +1cfftguu ** data written to the asci transmit data register is transferred to the 654 as soon as 654 is empty. data can be written while 654 is shifting out the previous byte of data. thus, the asci transmitter is double buffered. (kiwtg #5%+$nqem&kcitco +pvgtpcn#fftguu&cvc$wu #5%+6tcpuokv&cvc4gikuvgt %j 6&4 #5%+6tcpuokv5jkhv4gikuvgt #5%+4gegkxg&cvc(+(1 %j 4&4 #5%+4gegkxg5jkhv4gikuvgt %j 454 #5%+%qpvtqn4gikuvgt# %j %06.# #5%+%qpvtqn4gikuvgt$ %j %06$ #5%+5vcvwu4gikuvgt %j 56#6 #5%+'zvgpukqp%qpvtqn4gi %j #5':6 #5%+6kog%qpuvcpv.qy %j #56%. #5%+6kog%qpuvcpv*kij %j #56%* #5%+5vcvwu(+(1 %j #5%+6tcpuokv&cvc4gikuvgt %j 6&4 #5%+6tcpuokv5jkhv4gikuvgt #5%+4gegkxg&cvc(+(1 %j 4&4 #5%+4gegkxg5jkhv4gikuvgt %j 454 #5%+%qpvtqn4gikuvgt# %j %06.# #5%+%qpvtqn4gikuvgt$ %j %06$ #5%+5vcvwu4gikuvgt %j 56#6 #5%+'zvgpukqp%qpvtqn4gi %j #5':6 #5%+6kog%qpuvcpv.qy %j #56%. #5%+6kog%qpuvcpv*kij %j #56%* #5%+5vcvwu(+(1 %j 6:# 4:# 465 %65 &%& 6:# 4:# %65 #5%+ %qpvtqn $cwf4cvg )gpgtcvqt $cwf4cvg )gpgtcvqt %-# %-# 2*+ 0qvg 0qv2tqitco +pvgttwrv4gswguv #eeguukdng <5<. zilog 'pjcpegf</ketqrtqeguuqt &5454 this register receives data shifted in on the 4:# pin. when full, data is automatically transferred to the asci receive data regis- ter ( 4&4 ) if it is empty. if 454 is not empty when the next incoming data byte is shifted in, an overrun error occurs. this register is not program accessible. #5%+4gegkxg&cvc(+(1 4&4 +1#fftguu ** the asci receive data register is a read-only register. when a complete incoming data byte is assembled in 454 , it is automatically transferred to the 4 character re- ceive data first-in first-out ( (+(1 ) memory. the oldest character in the (+(1 (if any) can be read from the receive data register ( 4&4 ). the next incoming data byte can be shifted into 454 while the (+(1 is full. thus, the asci re- ceiver is well buffered. #5%+56#675(+(1 this four-entry (+(1 contains parity error, framing error, rx overrun, and break status bits associated with each char- acter in the receive data (+(1 . the status of the oldest char- acter (if any) can be read from the asci status registers. #5%+%*#00'.%10641.4')+56'4# /2' /wnvk2tqeguuqt/qfg'pcdng $kv the asci features a multiprocessor communication mode that utilizes an extra data bit for selective communication when a num- ber of processors share a common serial bus. multiproces- sor data format is selected when the /2 bit in %06.$ is set to 1 . if multiprocessor mode is not selected ( /2 bit in %06.$ ), /2' has no effect. if multiprocessor mode is selected, /2' enables or disables the wake-up feature as follows. if /$' is set to 1 , only received bytes in which the multiprocessor bit ( /2$ ) can affect the 4&4( and error flags. effectively, other bytes (with /2$ ) are ignored by the asci. if /2' is reset to 0 , all bytes, regardless of the state of the /2$ data bit, affect the 4'&4 and error flags. /2' is cleared to 0 during 4'5'6 . 4' 4gegkxgt'pcdng $kv when 4' is set to 1 , the asci transmitter is enabled. when 6' is reset to 0 , the transmitter is disables and any transmit operation in progress is inter- rupted. however, the 6&4' flag is not reset and the previous contents of 6&4' are held. 6' is cleared to 0 in +15612 mode during 4'5'6 . 6' 6tcpuokvvgt'pcdng $kv when 6' is set to 1 , the asci receiver is enabled. when 6' is reset to 0 , the trans- mitter is disabled and any transmit operation in progress is interrupted. however, the 6&4' flag is not reset and the pre- (kiwtg #5%+%jcppgn%qpvtqn4gikuvgt# $kv /2' 4' 49 49 49 6' 465 /2$4 /1& /1& /1& 49 49 #5%+%qpvtqn4gikuvgt# %06.# +1#fftguu * 49 49 49 '(4 $kv /2' 4' 49 49 49 6' /1& /1& /1& 49 49 #5%+%qpvtqn4gikuvgt# %06.# +1#fftguu * 49 49 49 /2$4 '(4 %-#& <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf vious contents of 6&4' are held. 6' is cleared to 0 in +15612 mode during 4'5'6 . 465 4gswguv vq 5gpf %jcppgn $kv kp %06.# 1pn[ if bit 4 of the system configuration register is 0 , the 465 / 6:5 pin exhibits the 465 function. 465 allows the asci to control (start/stop) another communication de- vices transmission (for example, by connecting to that de- vices %65 input). 465 is essentially a 1-bit output port, having no side effects on other asci registers or flags. bit 4 in %06.# is used. %-#& %-#6'0& rkp 6'0& %-#& , %-#6'0& rkp %-# these bits are cleared to 0 on reset. /2$4'(4 /wnvkrtqeguuqt$kv4gegkxg'ttqt(nci4gugv $kv when multiprocessor mode is enabled ( /2 in %06.$ ), /2$4 , when read, contains the value of the /2$ bit for the most recent receive operation. when written to 0 , the '(4 function is selected to reset all error flags ( 1840 , (' , 2' and $4- in the #5':6 register) to 0 . /2$4 / '(4 is undefined during 4'5'6 . /1& #5%+&cvc(qtocv/qfg dkvu these bits program the asci data format as follows. /1& ? dkvfcvc ? dkvfcvc /1& ? 0qrctkv[ ? 2ctkv[gpcdngf /1& ? uvqrdkv ? uvqrdkvu the data formats available based on all combinations of /1& , /1& , and /1& are indicated in table 9. 6cdng &cvc(qtocvu /1& /1& /1& &cvc(qtocv 5vctv dkvfcvc uvqr 5vctv dkvfcvc uvqr 5vctv dkvfcvc rctkv[ uvqr 5vctv dkvfcvc rctkv[ uvqr 5vctv dkvfcvc uvqr 5vctv dkvfcvc uvqr 5vctv dkvfcvc rctkv[ uvqr 5vctv dkvfcvc rctkv[ uvqr <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kv when multi- processor communication format is selected ( /2 bit = ), /2$6 is used to specify the /2$ data bit for transmission. if /2$6 1 , then /2$ is transmitted. if /2$6 0 , then /2$ 0 is transmitted. the /2$6 state is unde- fined during and after 4'5'6 . /2 /wnvkrtqeguuqt/qfg $kv when /2 is set to 1 , the data format is configured for multiprocessor mode based on /1& (number of data bits) and /1& (number of stop bits) in %06.# . the format is as follows: 5vctvdkv qtfcvcdkvu /2$dkv qtuvqrdkvu multiprocessor ( /2 ) format offers no provision for parity. if /2 0 , the data format is based on /1& , /1& , /1& , and may include parity. the /2 bit is cleared to 0 during 4'5'6 . %65 25 %ngctvq5gpf2tguecng $kv when read, %65 25 reflects the state of the external %65 input. if the %65 input pin is high, %65 25 is read as 1 . 0qvg when the %65 input pin is high, the 6&4' bit is inhib- ited (that is, held at ). for channel 1, the %65 input is multiplexed with 4:5 pin (clocked serial receive data). thus, %65 25 is only valid when read if the channel 1 %65' bit = 1 and the %65 input pin function is selected. the 4'#& data of %65 25 is not affected by 4'5'6 . if the 55 bits in this register are not , and the $4) mode bit in the #5':6 register is 0 , then writing to this bit sets the prescale (ps) control. under those circumstances, a 0 indicates a divide-by-10 prescale function while a 1 indicates divide-by-30. the bit resets to 0 . 2'1 2ctkv['xgp1ff $kv 2'1 selects oven or odd parity. 2'1 does not affect the enabling/disabling of parity ( /1& bit of %06.# ). if 2'1 is cleared to 0 , even parity is selected. if 2'1 is set to 1 , odd parity is selected. 2'1 is cleared to 0 during 4'5'6 . &4 &kxkfg4cvkq $kv if the : bit in the #5':6 reg- ister is 0 , this bit specifies the divider used to obtain baud rate from the data sampling clock. if &4 is reset to 0 , divide- by-16 is used, while if &4 is set to 1 , divide-by-64 is used. &4 is cleared to 0 during 4'5'6 . 55 5qwteg5rggf5gngev $kvu first, if these bits are , as they are after a 4'5'6 , the %-# pin is used as a clock input, and is divided by 1, 16, or 64 depending on the &4 bit and the : bit in the #5':6 reg- ister. if these bits are not and the $4) mode bit is #5':6 is 0 , then these bits specify a power-of-two divider for the 2*+ clock as indicated in table 10. setting or leaving these bits as makes sense for a chan- nel only when its %-# pin is selected for the %-# function. %-#1%-5 offers the %-#1 function when bit 4 of the sys- tem configuration register is 0 . &%& / %-# offers the %-# function when bit 0 of the interrupt edge register is 1 . (kiwtg #5%+%jcppgn%qpvtqn4gikuvgt$ $kv /2$6 /2 49 49 49 %65 2'1 &4 55 55 55 49 49 #5%+%qpvtqn4gikuvgt$ %06.$ +1#fftguu * 49 49 49 #5%+%qpvtqn4gikuvgt$ %06.$ +1#fftguu * 25 6cdng &kxkfg4cvkq 55 55 55 &kxkfg4cvkq ? ? ? ? ? ? ? 'zvgtpcn%nqem <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5$kv 4&4( is set to 1 when an incoming data byte is loaded into an empty 4z (+(1 . if a framing or parity error occurs, 4&4( is still set and the receive data (which generated the error) is still load- ed into the (+(1 . 4&4( is cleared to 0 by reading 4&4 and most recently received character in the (+(1 from +15612 mode, during 4'5'6 and for #5%+ if the &%& input is auto-enabled and is negated (high). 1840 1xgttwp'ttqt $kv an overrun condition oc- curs if the receiver finishes assembling a character but the 4z(+(1 is full so there is no room for the character. how- ever, this status bit is not set until the most recent character received before the overrun becomes the oldest byte in the (+(1 . this bit is cleared when software writes a 1 to the '(4 bit in the %06.# register. the bit may also be cleared by 4'5'6 in +15612 mode or #5%+ if the &%& pin is auto enabled and is negated (high). 0qvg when an overrun occurs, the receiver does not place the character in the shift register into the (+(1 , nor any sub- sequent characters, until the most recent good character enters the top of the (+(1 so that 1840 is set. software then writes a 1 to '(4 to clear it. 2' 2ctkv['ttqt $kv a parity error is detected when parity checking is enabled.when the /1& bit in the %06.# register is 1 , a character is assembled in which the parity does not match the 2'1 bit in the %06.$ register. however, this status bit is not set until or unless the error character becomes the oldest one in the 4z(+(1 . 2' is cleared when software writes a 1 to the '(4 bit in the %064.# register. 2' is also cleared by 4'5'6 in +15612 mode, or on #5%+ , if the &%& pin is auto-enabled and is negated (high). (' (tcokpi'ttqt $kv a framing error is detected when the stop bit of a character is sampled as 52#%' . however, this status bit is not set until/unless the error char- acter becomes the oldest one in the 4z(+(1 . (' is cleared when software writes a 1 to the '(4 bit in the %06.# reg- ister. (' is also cleared by 4'5'6 in +15612 mode, or on #5%+ , if the &%& pin is auto-enabled and is negated (high). 4'+ 4gegkxg+pvgttwrv'pcdng $kv 4+' should be set to 1 to enable asci receive interrupt requests. when 4+' is 1 , the receiver requests an interrupt when a character is re- ceived and 4&4( is set, but only if neither dma channel requires its request-routing field to be set to receive data from this asci. that is, if 5/ are and 5#4 are , or &+/ is 1 and +#4 are , then asci1 does not request an interrupt for 4&4( . if 4+' is 1 , either asci requests an interrupt when 1840 , 2' or (' is set, and (kiwtg #5%+5vcvwu4gikuvgtu $kv 4&4( 1840 4449 2' (' 4' &%& 6&4' 6+' 4 4 #5%+5vcvwu4gikuvgt 56#6 +1#fftguu * 4449 $kv 4&4( 1840 449 2' (' 4' 6&4' 6+' 44 #5%+5vcvwu4gikuvgt 56#6 +1#fftguu * 4449 %65' 49 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kv56#6 this bit is set to 1 when the pin is high. it is cleared to 0 on the first 4'#& of 56#6 following the pin's transition from high to low and during 4'5'6 . when bit 6 of the #5':6 reg- ister is 0 to select auto-enabling, and the pin is negated (high), the receiver is reset and its operation is inhibited. %65' %ngct6q5gpf $kv56#6 channel 1 fea- tures an external %65 input, which is multiplexed with the receive data pin 45: for the csi/o. setting this bit to 1 selects the %65 function; clearing the bit to 0 selects the 4:5 function. 6&4' 6tcpuokv&cvc4gikuvgt'orv[ $kv 6&4' 1 indicates that the 6&4 is empty and the next transmit data byte is written to 6&4 . after the byte is written to 6&4 , 6&4' is cleared to 0 until the asci transfers the byte from 6&4 to the 654 and then 6&4' is again set to 1 . 6&4' is set to 1 in +15612 mode and during 4'5'6 . on asci0, if the %65 pin is auto-enabled in the #5':6 register and the pin is high, 6&4' is reset to 0 . 6+' 6tcpuokv+pvgttwrv'pcdng $kv 6+' should be set to 1 to enable asci transmit interrupt requests. if 6+' 1 , an interrupt is requested when 6&4' 1 . 6+' is cleared to 0 during 4'5'6 . #5%+64#05/+6#4')+56'45 register addresses 06h and 07h hold the asci transmit data for channel 0 and channel 1, respectively. #5%+6tcpuokv&cvc4gikuvgtu%jcppgn /pgoqpke6&4 #fftguu* #5%+6tcpuokv&cvc4gikuvgtu%jcppgn /pgoqpke6&4 #fftguu* (kiwtg #5%+4gikuvgt #5%+6tcpuokv %jcppgn (kiwtg #5%+4gikuvgt #5%+6tcpuokv %jcppgn <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5$kv '( is set to 1 by the csi/o to indicate completion of an 8-bit data transmit or receive operation. if end interrupt enable ( '+' ) bit = 1 when '( is set to 1 , a cpu interrupt request is generated. program access of 64&4 only occurs if '( 1 . the csi/o clears '( to 0 when 64&4 is read or written. '( is cleared to 0 during 4'5'6 and +15612 mode. '+' 'pf+pvgttwrv'pcdng $kv '+' is set to 1 to gen- erate a cpu interrupt request. the interrupt request is in- hibited if '+' is reset to 0 . '+' is cleared to 0 during 4'5'6 . 4' 4gegkxg'pcdng $kv a csi/o receive operation is started by setting 4' to 1 . when 4' is set to 1 , the data clock is enabled. in internal clock mode, the data clock is output from the %-5 pin. in external clock mode, the clock is input on the %-5 pin. in either case, data is shifted in on the 4:5 pin in synchronization with the (internal or external) data clock. after receiving 8 bits of data, the csi/o automati- cally clears 4' to 0 , '( is set to 1 , and an interrupt (if enabled by '+' ) is generated. 4' and 6' are never both set to 1 at the same time. 4' is cleared to 0 during 4'5'6 and +15612 mode. 6' 6tcpuokv'pcdng $kv a csi/o transmit operation is started by setting 6' to 1 . when 6' is set to 1 , the data clock is enabled. when in internal clock mode, the data clock is output from the %-5 pin. in external clock mode, the clock is input on the %-5 pin. in either case, data is shift- ed out on the 6:5 pin synchronous with the (internal or ex- ternal) data clock. after transmitting 8 bits of data, the csi/o automatically clears 6' to 0 , sets '( to 1 , and re- quests an interrupt if enabled by '+' 1 . 6' and 4' are (kiwtg #5%+4gegkxg4gikuvgt%jcppgn #5%+6tcpuokv&cvc (kiwtg #5%+4gegkxg4gikuvgt%jcppgn #5%+6tcpuokv&cvc (kiwtg %5+1%qpvtqn4gikuvgt %064 +1#fftguu #* $kv '( '+' 49 49 49 4' 6' aa 55 55 55 4 49 49 49 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kvu 55 , 55 and 55 select the csi/o transmit/receive clock source and speed. 55 , 55 and 55 are all set to 1 during 4'5'6 . table 11 indicates csi/o baud rate selection. after 4'5'6 , the %-5 pin is configured as an external clock input ( 555555 ). changing these values causes %-5 to become an output pin and the selected clock is output when transmit or receive operations are enabled. %5+16tcpuokv4gegkxg&cvc4gikuvgt /pgoqpke64&4 #fftguu$* 6kogt&cvc4gikuvgt%jcppgn.qy /pgoqpke6/&4. #fftguu%* 6kogt&cvc4gikuvgt%jcppgn* /pgoqpke6/&4* #fftguu&* 6kogt4gnqcf4gikuvgt%jcppgn.qy /pgoqpke4.&4. #fftguu'* 6kogt4gnqcf4gikuvgt%jcppgn*kij /pgoqpke4.&4* #fftguu(* 6cdng %5+1$cwf4cvg5gngevkqp 55 55 55 &kxkfg4cvkq ? ? ? ? ? ? ? 'zvgtpcn%nqem+prwv .guu6jcp ? (kiwtg %5+16tcpuokv4gegkxg&cvc4gikuvgt (kiwtg 6kogt4gikuvgt%jcppgn.qy %5+164&cvc #5%+4gegkxg&cvc (kiwtg 6kogt&cvc4gikuvgt%jcppgn*kij (kiwtg 6kogt4gnqcf4gikuvgt.qy (kiwtg 6kogt4gnqcf4gikuvgt%jcppgn*kij 6kogt&cvc 6kogt4gnqcf&cvc 6kogt4gnqcf&cvc <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5$kv when 6/&4 dec- rements to 0 , 6+( is set to 1 . this condition generates an interrupt request if enabled by 6+' 1 . 6+( is reset to 0 when 6%4 is read and the higher or lower byte of 6/&4 is read. during 4'5'6 , 6+( is cleared to 0 . 6+( 6kogt+pvgttwrv(nci $kv when 6/&4 dec- rements to 0 , 6+( is set to 1 . this condition generates an interrupt request if enabled by 6+' 1 . 6+( is reset to 0 when 6%4 is read and the higher or lower byte of 6/&4 is read. during 4'5'6 , 6+( is cleared to 0 . 6+' 6kogt+pvgttwrv'pcdng $kv when 6+' is set to 1 , 6+( 1 generates a cpu interrupt request. when 6+' is reset to 0 , the interrupt request is inhibited. during 4'5'6 , 6+' is cleared to 0 . 61% 6kogt1wvrwv%qpvtqn $kvu 61% and 61% control the output of 246 using the multiplexed #6 176 pin as indicated in table 12. during 4'5'6 , 61% and 61% are cleared to 0 . if bit 3 of the +#4$ reg- ister is 1 , the 6 176 function is selected. by programming 61% and 61% , the #6 176 pin can be forced high, low, or toggled when 6/&4 decrements to 0 . 6&' 6kogt&qyp%qwpv'pcdng $kvu 6&' and 6&' enable and disable down-counting for 6/&4 and 6/&4 , respectively. when 6&'p ( p , ) is set to 1 , down-counting is stopped and 6/&4p is freely read or written. 6&' and 6&' are cleared to 0 during 4'5'6 and 6/&4p does not decrement until 6&'p is set to . (kiwtg 6kogt%qpvtqn4gikuvgt 6%4 +1#fftguu * $kv 6+( 6+( 49 49 49 6+' 6+' 61% 6&' 6&' 4 4 49 49 49 61% 6cdng 6kogt1wvrwv%qpvtqn 61% 61% 1wvrwv +pjkdkvgf 6jg#6 176 rkpkupqv chhgevgfd[vjg246 6qiingf +hdkvqh+#4$kuvjg #6 176 rkpkuvqiingfqt ugv.qyqt*kijcu kpfkecvgf <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kv#5%+1pn[ if this bit is 0 , then the &%& pin auto-enables the asci0 receiver, such that when the pin is negated/high, the receiver is held in a 4' 5'6 state. if this bit is 1 , the state of the &%& -pin has no effect on receiver operation. in either state of this bit, soft- ware can read the state of the &%& pin in the 56#6 reg- ister, and the receiver interrupts on a rising edge of &%& . %65&kucdng $kv#5%+1pn[ if this bit is 0 , then the %65 pin auto-enables the #5%+1 transmitter, in that when the pin is negated/high, the 6&4' bit in the 56#6 register is forced to 0 . if this bit is 1 , the state of the %65 pin has no effect on the transmitter. regardless of the state of this bit, software can read the state of the %65 pin the %06.$ register. : $kv if this bit is 1 , the clock from the baud rate generator or %-# pin is taken as a 1x-bit clock (sometimes called isochronous mode ). in this mode, receive data on the 4:# pin must be synchronized to the clock on the %-# pin, regardless of whether %-# is an input or an output. if this bit is 0 , the clock from the baud rate generator or %-# pin is divided by 16 or 64 per the &4 bit in the %06.$ reg- ister, to obtain the actual bit rate. in this mode, receive data on the 4:# pin is not required to be synchronized to a clock. $4)/qfg $kv if the 55 bits in the %06.$ register are not , and this bit is 0 , the asci baud rate generator divides 2*+ by 10 or 30, depending on the 25 bit in %06.$ , and factored by a power of two (selected by the 55 bits), to obtain the clock that is presented to the transmitter and receiver and output on the %-# pin. if 55 are not , and this bit is 1 , the baud rate generator divides 2*+ by twice the sum of the 16-bit value (programmed into the time constant registers) and 2. this mode is identical to the operation of the baud rate generator in the '5%% . $tgcm'pcdng $kv if this bit is 1 , the receiver detects $4'#- conditions and report them in bit 1 , and the trans- mitter sends $4'#- s under the control of bit 0 . $tgcm&gvgev $kv the receiver sets this read-only bit to 1 when an all-zero character with a framing error becomes the oldest character in the 4z(+(1 . the bit is cleared when software writes a 0 to the '(4 bit in %06.# register, also by 4'5'6 , by +15612 mode, and for #5%+ , if the &%& pin is auto-enabled and is negated (high). 5gpf$tgcm $kv if this bit and bit 2 are both 1 , the trans- mitter holds the 6:# pin low to send a $4'#- condition. the duration of the $4'#- is under software control (one of the prts or ctcs can be used to time it). this bit resets to 0 , in which state 6:# carries the serial output of the trans- mitter. (kiwtg #5%+'zvgpukqp%qpvtqn4gikuvgtu%jcppgnucpf $kv &%& : $4) $tgcm $tgcm 5gpf #5%+'zvgpukqp%qpvtqn4gikuvgt #5':6+1#fftguu * %65 /qfg 'pcdng $tgcm $kv : $4) $tgcm $tgcm 5gpf /qfg 'pcdng $tgcm #5%+'zvgpukqp%qpvtqn4gikuvgt #5':6+1#fftguu * 4gugtxgf 4gugtxgf 4gugtxgf 4gugtxgf &kucdng &kucdng <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%qpvkpwgf 6kogt&cvc4gikuvgt%jcppgn.qy /pgoqpke6/&4. #fftguu* 6kogt&cvc4gikuvgt%jcppgn*kij /pgoqpke6/&4* #fftguu* 6kogt4gnqcf4gikuvgt%jcppgn.qy /pgoqpke4.&4. #fftguu 6kogt4gnqcf4gikuvgt%jcppgn*kij /pgoqpke4.&4* #fftguu* (tgg4wppkpi%qwpvgt 4gcf1pn[ /pgoqpke(4% #fftguu* (kiwtg 6kogt&cvc4gikuvgt.qy (kiwtg 6kogt&cvc4gikuvgt*kij (kiwtg 6kogt4gnqcf%jcppgn.qy 6kogt&cvc 6kogt&cvc 4gnqcf&cvc (kiwtg 6kogt4gnqcf4gikuvgt%jcppgn*kij (kiwtg (tgg4wppkpi%qwpvgt 4gnqcf&cvc %qwpvkpi&cvc <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 6% zucornkpitcvg where 6% is the 16-bit value programmed into the asci time constant high and low registers. if the asci multi- plexed %-# pin is selected for the %-# function, it outputs the clock before the final division by the sampling rate, as follows: h %-#qwv h 2*+ 6% find the 6% value for a particular serial bit rate as follows: 6% h 2*+ zdkvuugeqpfzucornkpitcvg (kiwtg #5%+6kog%qpuvcpv4gikuvgtu $kv $kv #5%+6kog%qpuvcpv4gikuvgt.qy #56%.+1#fftguu#* #5%+6kog%qpuvcpv4gikuvgt.qy #56%.+1#fftguu%* #5%+6kog%qpuvcpv4gikuvgt*kij #56%*+1#fftguu$* #5%+6kog%qpuvcpv4gikuvgt*kij #56%*+1#fftguu&* .5$kvuqh6kog%qpuvcpv /5$kvuqh6kog%qpuvcpv <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5</27#fftguu'* $kv:%nqem/wnvkrnkgt/qfg when this bit is set to 1 , the programmer can double the internal clock speed from the speed of the external clock. this feature only operates effectively with frequencies of 10C16 mhz (20C32 mhz in- ternal). when this bit is set to 0 , the z8s180/z8l180 device operates in normal mode. at power-up, this feature is dis- abled. $kv.qy0qkug%t[uvcn1rvkqp setting this bit to 1 en- ables the low-noise option for the ':6#. and :6#. pins. this option reduces the gain in addition to reducing the out- put drive capability to 30% of its original drive capability. the low noise crystal option is recommended in the use of crystals for pcmcia applications, where the crystal may be driven too hard by the oscillator. setting this bit to 0 is selected for normal operation of the ':6#. and :6#. pins. the default for this bit is 0 . 0qvg operating restrictions for device operation are listed be- low. if a low-noise option is required, and normal device operation is required, use the clock multiplier feature. (kiwtg %nqem/wnvkrnkgt4gikuvgt 4'5'48'& .1901+5'%4;56#. :%.1%-/7.6+2.+'4 6cdng .qy0qkug1rvkqp .qy0qkug #&&4'dkv 0qtocn #&&4'dkv /*\"8u% /*\"8u% /*\"8u% /*\"8u% <5<. zilog 'pjcpegf</ketqrtqeguuqt &5# $kv # &/#6tcpuhgt4gswguv &4'3 gzvgtpcn 4&4( #5%+ 4&4( #5%+ 4gugtxgf &/#%jcppgn#fftguu 4gugtxgf <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5# $kv # &/#6tcpuhgt4gswguv &4'3 gzvgtpcn 6&4 #5%+ 6&4 #5%+ 0qv7ugf # # 4gugtxgf <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5$kv when &' 1 and &/' 1 , channel 1 dma is enabled. when a dma transfer terminates ( $%4 ), &' is reset to 0 by the dmac. when &' 0 and the dma interrupt is enabled ( &+' 1 ), a dma interrupt request is made to the cpu. to perform a software 94+6' to &' , &9' should be written with a 0 during the same register 94+6' access. writing &' to 0 disables channel 1 dma, but dma is re- startable. writing &' to 1 enables channel 1 dma and automatically sets dma main enable ( &/' ) to 1 . &' is cleared to 0 during 4'5'6 . &' &/#'pcdng%jcppgn $kv when &' 1 and &/' 1 , channel 0 dma is enabled. when a dma transfer terminates ( $%4 ), &' is reset to 0 by the dmac. when &' 0 and the dma interrupt is enabled ( &+' 1 ), a dma interrupt request is made to the cpu. to perform a software 94+6' to &' , &9' should be written with 0 during the same register 94+6' access. writ- ing &' to 0 disables channel 0 dma. writing &' to 1 enables channel 0 dma and automatically sets dma main enable ( &/' ) to 1 . &' is cleared to 0 during 4'5'6 . &9' &'$kv9tkvg'pcdng $kv when performing any software 94+6' to &' , this bit should be written with 0 during the same access. &9' always reads as . &9' &'$kv9tkvg'pcdng $kv when performing any software 94+6' to &' , this bit should be written with 0 during the same access. &9' always reads as . &+' &/#+pvgttwrv'pcdng%jcppgn $kv when &+' is set to 1 , the termination channel 1 dma transfer (indicated when &' 0 ) causes a cpu interrupt request to be generated. when &+' 0 , the channel 0 dma ter- mination interrupt is disabled. &+' is cleared to 0 during 4'5'6 . &+' &/#+pvgttwrv'pcdng%jcppgn $kv when &+' is set to 1 , the termination channel 0 of dma transfer (indicated when &' ) causes a cpu interrupt request to be generated. when &+' 0 , the channel 0 dma ter- mination interrupt is disabled. &+' is cleared to 0 during 4'5'6 . &/' &/#/ckp'pcdng $kv a dma operation is only enabled when its &' bit ( &' for channel 0 , &' for channel 1) and the &/' bit is set to . when 0/+ occurs, &/' is reset to 0 , thus disabling dma activity during the 0/+ interrupt service routine. to restart dma, &' and/or &' should be written with a 1 (even if the contents are already ). this condition automatically sets &/' to 1 , allowing dma operations to continue. 0qvg &/' cannot be directly written. the bit is cleared to 0 by 0/+ or indirectly set to 1 by setting &' and/or &' to 1 . &/' is cleared to 0 during 4'5'6 . (kiwtg &/#5vcvwu4gikuvgt &56#6 +1#fftguu * $kv &' &' &9' 49 49 9 &9' &+' &+' &/' 9 49 49 4 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kvu this mode specifies whether the destination for channel 0 transfers is memory or i/o, and whether the address should be incre- mented or decremented for each byte transferred. &/ and &/ are cleared to 0 during 4'5'6 . 5/5/ 5qwteg/qfg%jcppgn $kvu this mode specifies whether the source for channel 0 transfers is memory or i/o, and whether the address should be incre- mented or decremented for each byte transferred. (kiwtg &/#/qfg4gikuvgt &/1&' +1#fftguu * $kv &/ &/ 49 49 5/ 5/ //1& 49 49 49 6cdng %jcppgn&guvkpcvkqp &/ &/ /goqt[+1 /goqt[ +petgogpv&getgogpv /goqt[ /goqt[ /goqt[ hkzgf +1 hkzgf 6cdng %jcppgn5qwteg 5/ 5/ /goqt[+1 /goqt[ +petgogpv&getgogpv /goqt[ /goqt[ /goqt[ hkzgf +1 hkzgf <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5$kv when chan- nel 0 is configured for memory to/from memory transfers there is no request handshake signal to control the transfer timing. instead, two automatic transfer timing modes are se- lectable: burst ( // 1& ) and cycle steal ( //1& ). for burst memory to/from memory transfers, the dmac takes control of the bus continuously until the dma transfer completes (as indicated by the byte count register = ). in cycle steal mode, the cpu is provided a cycle for each dma byte transfer cycle until the transfer is completed. for channel 0 dma with i/o source or destination, the se- lected request signal times the transfer ignoring //1& . //1& is cleared to 0 during 4'5'6 . 6cdng 6tcpuhgt/qfg%qodkpcvkqpu &/ &/ 5/ 5/ 6tcpuhgt/qfg #fftguu+petgogpv&getgogpv /goqt[ ? /goqt[ 5#4 /goqt[ ? /goqt[ 5#4 /goqt[ ? /goqt[ 5#4hkzgf +1 ? /goqt[ 5#4hkzgf /goqt[ ? /goqt[ 5#4 /goqt[ ? /goqt[ 5#4 /goqt[ ? /goqt[ 5#4hkzgf +1 ? /goqt[ 5#4hkzgf /goqt[ ? /goqt[ 5#4 hkzgf /goqt[ ? /goqt[ 5#4 hkzgf 4gugtxgf 4gugtxgf /goqt[ ? +1 5#4 hkzgf /goqt[ ? +1 5#4 hkzgf 4gugtxgf 4gugtxgf 0qvg * includes memory mapped i/o. <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kvu this bit specifies the number of wait states introduced into cpu or dmac memory access cycles. /9+ and /9+ are set to 1 during 4'5'6 . +9++9+ +19ckv+pugtvkqp $kvu this bit speci- fies the number of wait states introduced into cpu or dmac i/o access cycles. +9+ and +9+ are set to 1 during 4'5'6 . 0qvg these wait states are added to the 3-clock i/o cycle that is used to access the on-chip i/o registers. it is equally valid to regard these as 0 to 3 wait states added to a 4- clock external i/o cycle. &/5&/5 &/#4gswguv5gpug $kvu &/5 and &/5 specify the dma request sense for channel 0 and channel 1 respectively. when reset to 0 , the input is level sense. when set to 1 , the input is edge sense. &/5 and &/5 are cleared to 0 during 4'5'6 . typically, for an input/source device, the associated &/5 bit should be programmed as 0 for level sense. the device takes a relatively long time to update its request signal after the dma channel reads data (in the first of the two machine cycles involved in transferring a byte). an output/destination device takes much less time to update its request signal after the dma channel starts a 94+6' operation to it (the second machine cycle of the two cycles involved in transferring a byte). with zero-wait state i/o cy- cles, a device cannot update its request signal in the required time, so edge sensing must be used. a one-wait-state i/o cycle also does not provide sufficient time for updating, so edge sensing is again required. &+/ &+/ &/# %jcppgn +1 cpf /goqt[ /qfg $kvu specifies the source/destination and address modifier for channel 1 memory to/from i/o transfer modes. &+/ and &+/ are cleared to 0 during 4'5'6 . (kiwtg &/#9#+6%qpvtqn4gikuvgt &%06. +1#fftguu * $kv /9+ +9+ 49 49 &/5 &/5 &+/ 49 49 49 /9+ +9+ &+/ 49 49 49 /9+ /9+ 9ckv5vcvg +9+ +9+ 9ckv5vcvg &/5k 5gpug 'fig5gpug .gxgn5gpug 6cdng %jcppgn6tcpuhgt/qfg &+/ &/+ 6tcpuhgt/qfg #fftguu +petgogpv&getgogpv /goqt[ ? +1 /#4 +#4hkzgf /goqt[ ? +1 /#4 +#4hkzgf +1 ? /goqt[ +#4hkzgf/#4 +1 ? /goqt[ +#4hkzgf/#4 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5$kv this bit is set to 1 when an undefined op- code is fetched. 64#2 can be reset under program control by writing it with a ; however, 64#2 cannot be written with 1 under program control. 64#2 is reset to 0 during 4'5'6 . 7(1 7pfghkpgf(gvej1dlgev $kv when a 64#2 in- terrupt occurs, the contents of 7(1 allow the starting ad- dress of the undefined instruction to be determined. this in- terrupt is necessary because the 64#2 may occur on either the second or third byte of the opcode. 7(1 allows the stacked pc value to be correctly adjusted. if 7(1 0 , the first opcode should be interpreted as the stacked 2% . if 7(1 1 , the first opcode address is stacked 2% . 7(1 is read-only. +6' +pvgttwrv'pcdng $kvu +6' and +6' enable and disable the external interrupt inputs +06 and +06 , respectively. +6' enables and disables in- terrupts from: '5%% ? bidirectional centronics controller %6%u ? external interrupt input +06 a 1 in a bit enables the corresponding interrupt level while a 0 disables it. a 4'5'6 sets +6' to 1 and clears +6' and +6' to 0 . 64#2+pvgttwrv the z8s180/z8l180 generates a 64#2 sequence when an undefined opcode fetch occurs. this fea- ture can be used to increase software reliability, implement an extended instruction set, or both. 64#2 may occur during opcode fetch cycles and also if an undefined opcode is fetched during the interrupt acknowledge cycle for +06 when mode is used. when a 64#2 sequence occurs, the z8s180/z8l180: 1. sets the 64#2 bit in the interrupt 64#2 /control ( +6% ) register to 1 . 2. saves the current program counter (pc) value, reflecting the location of the undefined opcode, on the stack. 3. resumes execution at logical address 0 . 0qvg if logical address 0000h is mapped to physical address 00000h , the vector is the same as for 4'5'6 . in this case, testing the 64#2 bit in +6% reveals whether the re- start at physical address 00000h was caused by 4'5'6 or 64#2 . (kiwtg +pvgttwrv8gevqt.qy4gikuvgt +. +1#fftguu * $kv +. +. +pvgttwrv5qwteg&grgpfgpv%qfg +. 49 49 49 2tqitcoocdng $kv 64#2 7(1 49 49 49 +6' +6' +6' 49 4 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5# 2*+ & & 2% * 52 7pfghkpgf /4'3 / 4& 94 6 52 1reqfg 2% * 2% . pf1reqfg (gvej%[eng 2%5vcemkpi 1reqfg (gvej%[eng 4guvctv htqo* <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5# 2*+ & & 2% * 52 7pfghkpgf /4'3 / 4& 94 6 52 1reqfg 2% * 2% . tf1reqfg (gvej%[eng 2%5vcemkpi 1reqfg (gvej%[eng 4guvctv /goqt[ +: f+; f 6 k 6 k 4gcf%[eng (tqo* <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kv 4'(' 0 disables the re- fresh controller, while 4'(' 1 enables refresh cycle in- sertion. 4'(' is set to 1 during 4'5'6 . 4'(9 4ghtguj9ckv $kv 4'(9 0 causes the re- fresh cycle to be two clocks in duration. 4'(9 1 causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle ( 649 ). 4'(9 is set to 1 during 4'5'6 . %;% %[eng+pvgtxcn $kv %;% and %;% specify the interval (in clock cycles) between refresh cycles. when dynamic ram requires 128 refresh cycles every 2 ms (or 256 cycles in every 4 ms), the required refresh in- terval is less than or equal to 15.625 s. thus, the underlined values indicate the best refresh interval depending on cpu clock frequency. %;% and %;% are cleared to 0 during 4'5'6 (see table 18). 4ghtguj%qpvtqncpf4gugv after 4'5'6 , based on the initialized value of 4%4 , refresh cycles occur with an inter- val of 10 clock cycles and be 3 clock cycles in duration. &[pcoke4#/4ghtguj1rgtcvkqp 1. refresh cycle insertion is stopped when the cpu is in the following states: a. during 4'5'6 b. when the bus is released in response to $754'3 c. during 5.''2 mode d. during 9#+6 states 2. refresh cycles are suppressed when the bus is released in response to $754'3 . however, the refresh timer continues to operate. the time at which the first refresh cycle occurs after the z8s180/z8l180 reacquires the bus depends on the refresh timer. this cycle offers no timing relationship with the bus exchange. 3. refresh cycles are suppressed during 5.''2 mode. if a refresh cycle is requested during 5.''2 mode, the refresh cycle request is internally latched (until replaced with the next refresh request). the latched refresh cycle is inserted at the end of the first machine cycle after 5.''2 mode is exited. after this initial cycle, the time at which the next refresh cycle occurs depends on the refresh time and offers no relationship with the exit from 5.''2 mode. 4. the refresh address is incremented by one for each successful refresh cycle, not for each refresh. thus, independent of the number of missed refresh requests, each refresh bus cycle uses a refresh address incremented by one from that of the previous refresh bus cycles. (kiwtg 4ghtguj%qpvtqn4gikuvgt 4%4 +1#fftguu * 4gugtxgf %[e %[e 4'(9 4'(' 6cdng &4#/4ghtguj+pvgtxcnu 6kog+pvgtxcn %;% %;% +pugtvkqp+pvgtxcn 2*+ /*\ /*\ /*\ /*\ /*\ uvcvgu zu zu zu zu zu uvcvgu zu zu zu zu zu uvcvgu zu zu zu zu zu uvcvgu zu zu zu zu zu 0qvg *calculated interval. <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5%$4 +1#fftguu * $kv %$ %$ 49 %$ %$ %$ %$ %$ 49 %$ 49 49 49 49 49 49 (kiwtg //7$cpm$cug4gikuvgt $$4 +1#fftguu * $kv $$ $$ 49 $$ $$ $$ $$ $$ 49 $$ 49 49 49 49 49 49 (kiwtg //7%qooqp$cpm#tgc4gikuvgt %$#4 +1#fftguu #* $kv %# %# 49 %# %# $# $# $# 49 $# 49 49 49 49 49 49 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5$kvu %# specifies the start (low) ad- dress (on 4-kb boundaries) for common area 1. this con- dition also determines the most recent address of the bank area. all bits of %# are set to 1 during 4'5'6 . $# $# $kvu $# specifies the start (low) address (on 4-kb boundaries) for the bank area. this condition also determines the most recent address of common area 0 . all bits of $# are set to 1 during 4'5'6 . 12'4#6+10/1&'%10641.4')+56'4 the z8s180/z8l180 is descended from two different an- cestor processors, zilog's original z80 and the hitachi 64180. the operating mode control register ( 1/%4 ) can be programmed to select between certain differences be- tween the z80 and the 64180. 1rgtcvkqp/qfg%qpvtqn4gikuvgt /pgoqpke1/%4 #fftguu'* /' / 'pcdng this bit controls the / output and is set to a 1 during reset. when /' 1 , the / output is asserted low during the opcode fetch cycle, the +06 acknowledge cycle, and the first machine cycle of the 0/+ acknowledge. on the z8s180/z8l180, this choice makes the processor fetch one 4'6+ instruction. when fetching a 4'6+ from zero- wait-state memory, the processor uses three clock machine cycles that are not fully z80-timing-compatible. when /' 0 , the processor does not drive / low dur- ing instruction fetch cycles. after fetching one 4'6+ instruc- tion with normal timing, the processor returns and refetches the instruction using z80-compatible cycles that drive / low. this timing compatibility may be required by external z80 peripherals to properly decode the 4'6+ instruction. (kiwtg 1rgtcvkpi%qpvtqn4gikuvgt 1/%4 +1#fftguu '* & 4gugtxgf & & +1% 49 /6' 9 /' 49 (kiwtg 4'6++puvtwevkqp5gswgpegykvj/' t 1 t 2 t 3 t 1 t 2 t 3 t i t i t i t 1 t 2 t 3 t 1 t 2 t 3 t i t i a 0 Ca 18 (a 19 ) 2*+ d 0 Cd 7 pc pc+1 pc pc+1 edh 4dh edh 4dh mreq m1 rd st <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5$kvu +1# and +1# relocate internal i/o as indicated in figure 84. 0qvg the high-order 8 bits of 16-bit internal i/o address are al- ways 0 . +1# and +1# are cleared to 0 during 4'5'6 . +1562 +15612/qfg $kv +15612 mode is enabled when +1562 is set to 1 . normal i/o operation resumes when +1562 is reprogrammed or 4'5'6 to 0 . (kiwtg +1%qpvtqn4gikuvgt +%4 +1#fftguu (* +1# +1# +1562 $kv 49 49 49 (kiwtg +1#fftguu4gnqecvkqp +1# +1# +1# +1# +1# +1# +1# +1# ((* %* $(* * (* * (* * <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 <5<. 'pjcpegf</ketqrtqeguuqt zilog 24'.+/+0#4; &5 <5<. zilog 'pjcpegf</ketqrtqeguuqt &5 |
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